Clock and data recovery (CDR) circuits can be used with various communication protocols to generate a synchronized clock signal from received data. CDR circuits can allow for high speed data streams to be sent without a separate, dedicated, clock signal. For instance, a CDR circuit can be configured to infer clock signal timings (phase and frequency) from received data in the analog realm and make adjustments directly to a phase locked loop (PLL) or a delay locked loop (DLL). Certain types of CDR circuits can be configured to be based upon phase interpolation (PI) in which a set of reference clock signals are used to produce different phases. The CDR circuit selects the appropriate clock signal phases based upon the received data. There are a variety of different applications that can use CDR circuits including, but not limited to, programmable logic devices (PLDs).
PLDs are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay locked loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile can include both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are often programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
The internal delay or latency of CDR circuits, in various implementations, can have significant impact to the system performance. A CDR circuit that is configured to provide phase control signals from received data with a low latency can be useful for addressing such issues.